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| TSM006 Primary PWM Controller s s s s s s s s s s s s s s Current-mode PWM Controller High-current output drive suitable for Power MOSFET Automatic burst mode in zero-load condition Primary overcurrent protection (hiccup mode) Internal leading edge blanking on current sense External slope compensation capability Programmable soft start Frequency modulation for low emi Accurate oscillator frequency 77% duty cycle limitation 5V reference Under voltage protection Thermal shutdown at 130C 2kV ESD protection D SO-14 (Plastic MicroPackage) PIN CONNECTIONS (top view) DESCRIPTION The TSM006 integrated circuits incorporate all circuitry to implement off line or DC-DC power supply applications using a fixed frequency current mode control. Based on a standard current mode PWM controller, these devices include additional features for higher integration. 1 Rt/Ct 2 Fm 3 Cs 4 Bl 5 Ss 6 Comp 7 Bs Dis 14 Rex 13 Vref Vin Out Pgnd Cslope 12 11 10 9 8 APPLICATION s AC/DC adapter D = Small Outline Package (SO) - also available in Tape & Reel (DT) ORDER CODES Part Number TSM006ID TSM006IDT Temperature Range 0, +105C Package SO Packaging Tube Tape & Reel Marking TSM006 TSM006 July 2004 Revision 1 1/13 TSM006 1 Block Diagram Block Diagram 14 DIS Disable_Latch Thermal Shutdown Vin Hiccup_Latch Icomp 600A UVLO Standby Vref Vref 12 Cref Vref_Status BS 7 4 6 BL Burst_Latch 2R Comp 1V R Comp_Cs 28V 3 Cs Comp Clamp = Vss LEB Vref Rt 8 Cslope Slop_Compensation Vin 11 1 Ct Rt/Ct Comp_Osc Idct1 300A Cs_Latch R S Q !Q Out 10 Rb Fm 2 Cfm Iiss 10A S !Q 9 Pgnd Vref Frequency mod. 0.5V Comp_Hiccup R Q Start up_Latch 5 Css Soft start Ss Idss1 1A Idss2 1mA Current source REX 13 Rex PIN DESCRIPTION Name RT/CT FM CS BL SS COMP BS CSLOPE PGND OUT VIN VREF REX DIS SO14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Type Timing capacitor Analog input Analog input Analog output Timing capacitor Analog input Output input Analog output Power supply Analog output Power supply Analog output Analog input Analog input Function Sets the oscillator frequency and maximum duty cycle Frequency modulation Current sense. Burst level Soft start and hiccup timing, latched disable input. Current comparator for current mode control. Burst mode status Slope compensation Power ground Totem pole output to direct drive a power MOSFET. Supply input voltage. +5V Voltage reference External resistor for internal constant current Latched disable 2/13 Absolute Maximum Ratings 2 Absolute Maximum Ratings Symbol Vin Io Iopeak Vcomp Isinkcomp Vss Vout Vter Pt Tstg Tj ESD 1) TSM006 DC Supply Voltage DC Supply Voltage (Iin<50mA) DC output current Peak output current COMP terminal voltage COMP terminal sink current SS terminal voltage OUT terminal voltage Other terminal voltage (CT, VREF, BS, BL, CSLOPE REX, CS, FM, DIS) Power dissipation at 25C Storage temperature Junction temperature Electrostatic Discharge 1 Value -0.3 to self limit 0.1 1 -0.3 to 6.5 6 -0.3 to 8 -0.3 to Vin -0.3 to Vref 500 -40 to 150 150 2 Unit V A A V mA V V V mW C C kV All voltage values, except differential voltage are with respect to network ground terminal (GND). OPERATING CONDITIONS Symbol Vcc Toper Parameter DC Supply Conditions Operating Free Air Temperature Range Value 8 to 20 0 to 105 Unit V C 3/13 TSM006 3 Electrical Characteristics Symbol Main oscillator 8Vin20V, 0Ta105C Fosco FoscL Fjit Ffm Vthct Vtlct Vct Idct1 Idct2 Disable Vdis Vref Vline Vload Vtotal Ios IsinkCP IsrcCP Comp Icomp Avcs Vz1 PSRR Source current Gain Maximum sensing voltage Power supply voltage rejection ratio Delay to output Vcomp=5V 0V Vcs 0.8V Vcomp=5V 8V Vin 20V Vcs = 0 to 2 V Vcomp = 2 V Iosink=20mA Iosink=200mA Iosource=20mA Iosource=200mA CL=1nF, 10% to 90% CL=1nF, 90% to 10% Vin=5V, Iosink=1mA Option 1 Option 1 Voltage threshold Voltage reference Line regulation Load regulation Total variation Short circuit current Sink current Source current Lower oscillating frequency Upper oscillating frequency Frequency jitter Frequency modulation Upper trip point Lower trip point Amplitude Discharge current Current at Ct in UVLO Vfm=GND Vfm=Vref Fjit=Fosco - FoscL Vfm=GND Vfm=GND Vfm=GND Vct=2V Vct=1V Parameter Test Condition Electrical Characteristics Tamb = 25C, Vin=15V, Rt=39k, Ct=470pF, Rex=27k, Cfm=1nF unless otherwise specified Min Typ Max Unit 63 57.6 6 68 62 7 4.5 3.0 1.4 1.6 300 3 2.65 5.00 5 10 5.00 73 66.4 8 kHz kHz kHz kHz V V V A mA V V mV mV V mA A mA 1 2.5 4.91 2.8 5.09 10 20 5.15 Vref reference pin 12V Vin 20V 1mA Iref 5mA Line, load, temp Vref=0 Vct=2.2V, VCslope=1V Vct=2.2V, VCslope=0V 4.85 10 Slope Compensation 90 2 0.5 2.85 0.9 0.6 3.00 1.0 70 0.7 3.15 1.1 mA Current sense V dB Leading edge blanking LEB Output VOL1 VOL2 VOH1 VOH2 tr tf VOL3 Fout DCmax Output low voltage 1 Output low voltage 2 Output high voltage 1 Output high voltage 2 Rise time Fall time UVLO saturation Output frequency Maximum Duty Cycle 0.8 Vin-2.0 Vin-3.0 70 40 Fosc 77.5 100 60 0.5 1.0 2.2 V V V V ns ns V kHz % 280 ns 4/13 Electrical Characteristics TSM006 Symbol Soft start Iiss dIiss Idss1 Idss2 Iiss/Idss1 VHss VLss VH VL Iin Iidle Istby Vclamp Burst Vbsol Iohbs Vbl1 Vbl1hyst Vbl2 Hiccup Vz2 Vhicc Parameter Test Condition Min Typ Max Unit A A A mA V V V V mA mA A V V A V V V Charge current Temperature stability Discharge current (hiccup) Sink current (uvlo) Charge/discharge ratio Clamp voltage Low voltage (uvlo) UVLO top threshold UVLO bottom threshold Operating current Supply current in idle mode Supply current in standby mode Clamp voltage Output low voltage Leakage current Threshold level on Comp to enter Burst mode Vbl1 Hysteresis Threshold level on Comp to exit burst mode Threshold level on Cs to enter Hiccup mode Threshold level on Ss to exit Hiccup mode Vss=2V 0C Ta 105C Vss=2V, Vcs=2V Vss=2V, Vin=7V 8 7 3 10 10 1 10 12 13 1.2 11 0.5 4 Vin=7V, Idss=1mA 11.5 8.0 CL=1nF Vcomp=1V Vin Supply current 22 1.15 1.25 0.5 1.35 V V 5/13 TSM006 4 Functional Description Output driver Functional Description TSM006: PWM Controller IC. UVLO function The Under Voltage Lock Out function disables the whole device when supply voltage is lower than the threshold. The OUT totem pole output is capable to sink and source more than 1.0A (peak) in order to direct drive a power MOSFET. Oscillator A capacitor from the RT/CT pin to GND and a resistor to the VREF set the oscillating frequency. The maximum duty cycle at the OUT pin is limited at 77%. Vref block The Vref block provides a 5V reference voltage. An internal Vref status signal is active when Vref is lower than 4.7V and is used to drive the output driver low when Vref is not valid. Frequency modulation A FM generator adds a small amount of jitter on the oscillator frequency in a way that reduces the conducted and radiated EMI. The FM frequency is set by an external capacitor connected to the FM pin. Current sense input A voltage proportional to the output inductor current is applied to the CS pin. The control IC uses this information to perform current mode control. The PWM function will be stopped if the CS pin voltage is greater than 1.0V. Slope compensation A buffered Rt/Ct voltage is brought to the Cslope pin. This signal is used to provide the necessary slope compensation. Current leading edge blanking An internal delay is built into the IC to mask the first 100ns of the current sense signal. This delay is made of a capacitor charged with a current source. The capacitor is discharged when CT reaches its maximum level. Soft start A capacitor from the SS pin to GND provides the soft start function. The capacitor starts to charge when VIN reaches the UVLO threshold and Vref is good. The soft start block enables the IC to start with a progressive PWM duty cycle. The soft start comparator drives the output driver low when the SS pin voltage is greater than the CT pin voltage minus one Vbe voltage. During soft start, the COMP pin voltage is clamped to the SS pin voltage plus two Vbe voltage, limiting the maximum peak current. COMP input This pin is connected to the current comparator for current mode control. The pin should be connected to the collector (primary side) of an optocoupler which anode (secondary side) is driven by the output of error amplifier. The COMP input is used to set the reference level for the current sense comparator. The current sense threshold is set to (Vcomp - 2 * Vbe) / 3. During the soft start period, COMP voltage is clamped to the SS pin plus two Vbe voltage. External reference pin An external resistor at REX pin sets the internal current reference. Startup latch The startup latch is set when the IC exits from standby mode or UVLO state. It is reset when the CT capacitor is discharged for the first time. 6/13 Functional Description Automatic burst mode Burst mode is used during light load condition to reduce the number of MOS switching, and thus reducing overall power dissipation. Light load condition is detected when COMP voltage is low. When COMP voltage is lower than a threshold VBL1 set by the external BL pin, the device output is forced to off state, providing minimum duty cycle and pulse skipping. The burst status is available on the BS pin to put other devices in standby mode when in light load condition. When COMP voltage (Vcomp) is higher than VBL2, the device operates in normal mode. Current is limited to (Vcomp-2*Vbe)/3 / Rshunt (Rshunt is the shunt resistor used to measure the primary current, Vbe is the forward voltage of a diode, and 3 is the R/2R network attenuation). Maximum current is 1V/Rshunt. When Vcomp becomes lower than VBL, device enters burst mode, PWM is stopped while Comp voltage is lower than VBL. As PWM is stopped, no more energy is transferred to the secondary side, output voltage is decreasing, and Vcomp (which is an image of the error comparator) tends to increase. As soon as Vcomp becomes just higher than VBL, PWM operation can resume for some cycles, so current in burst mode is limited to (VBL2*Vbe)/3 / Rshunt. TSM006 OverCurrent detection and Hiccup mode Overcurrent is detected when voltage at the CS pin is greater than Vz2=1.2V. To avoid false triggering, the overcurrent detection is delayed in the same way than the normal pulse by pulse current limitation. When overcurrent is detected, the device enters the hiccup mode. Output is switched off immediately and the soft start capacitor is discharged slowly. When the SS pin voltage goes below 0.5V, normal soft start is started. If the overcurrent is no more present, device operation is resumed normally, otherwise, overcurrent is detected again and the cycle is repeated until the overcurrent situation disappears. Duty cycle of the hiccup mode is set by the ratio of SS pin discharge and charge currents: 10% typ. With a typical capacitor Css=100nF, soft start delay is about 40ms and hiccup off-time is 400ms. Latched disable function Disable mode is entered when the DIS pin voltage is driven above 2.5V. Disable state is latched and can only be exit by driving the Vin power supply voltage under the UVLO level. Thermal shutdown The device operation is shut down when the internal temperature exceed 130C. Hysteresis provides stable working and shutdown states. 7/13 TSM006 Fig. 1: Detailed Internal Schematic Functional Description 2.5V Comp_Dis R Q UVLO !Q Standby Vref S Disable_Latch Vref 12 Cref 14 Dis Vz2=1.2V Thermal Shutdown Comp_0cp R S Q !Q Vref_Status Hiccup_Latch Vin Comp_burst Bs Bs_latch Icomp 600A Vbl2 4 BL Vbl1 6 Comp VF VF 2R R Comp_burst S !Q R Q 28V 7 Comp_Cs 1V Vref Rt Cs Rt/Ct Idct1 300A Idct2 1mA 1.4V-3.0V Comp_Osc LEB 3 1 Cs_Latch R S Q !Q Out 10 Vin 11 Ct Rb Vref Start up_Latch Cslope Vref 11k Iiss 10A 0.5V Frequency Modulation Comp_Hiccup FM 2 CFm R S Q !Q Pgnd 9 8 Comp_ss Current source 5 Css Ss Idss1 1A Idss2 1mA Rex 13 Rex 8/13 Timing Diagram 5 Timing Diagram TSM006 Timing for PWM function RT/CT COMP (COMP-2VF)/3 CS OUT Driving by maximum duty cycle Driving by PWM No output Timing at Vref rise up and shut down VH VL Vin 12V 8.4V 2V UVLO 4.7V Vref VrefStatus RT/CT Startup OUT 9/13 TSM006 Timing for soft start function Timing Diagram RT/CT 2VBE COMP CT-1VBE SS OUT Soft start period Max. duty cycle Timing for latched disable function VH VIN VL 2.5V DIS SS Disable Latch nQ OUT Soft start Active Shut-down Soft start Active 10/13 Timing Diagram Timing for burst mode function COMP VBL Max Current TSM006 VBL1 Current Level in Burst Mode CS BS OUT Normal mode Burst Mode Normal mode Timing for hiccup function OverCurrent Level Max Current CS Hiccup latch nQ SS 0.5V OUT Normal mode Hiccup mode Normal mode 11/13 TSM006 Timing for oscillator function Timing Diagram Vref FM (DAP009A only) Gnd RT/CT FM oscillation (Ffm=4.5kHz typ.) Foscl Fosco 62kHz typ. 68kHz typ. Fjit = Fosco - Foscl (6kHz typ.) 12/13 Timing Diagram PACKAGE MECHANICAL DATA SO-14 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 8.55 5.8 1.27 7.62 4.0 5.3 1.27 0.68 8 (max.) 0.149 0.181 0.019 8.75 6.2 0.35 0.19 0.5 45 (typ.) 0.336 0.228 0.050 0.300 0.157 0.208 0.050 0.026 0.344 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 TSM006 PO13G Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Repubic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 13/13 |
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